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ADE7754
Table VIII. Register List (continued)
Address
Default
[A5:A0] Name
R/W * Length
Value
Description
31h
32h
33h
34h
35h
CIrmsOS
AVrmsOS
BVrmsOS
CVrmsOS
AAPGAIN
R/W
R/W
R/W
R/W
R/W
12
12
12
12
12
0
0
0
0
0
Phase C Current RMS Offset Correction Register.
Phase A Voltage RMS Offset Correction Register.
Phase B Voltage RMS Offset Correction Register.
Phase C Voltage RMS Offset Correction Register.
Phase A Active Power Gain Adjust. The active power accumulation of the
Phase A can be calibrated by writing to this register. The calibration range
is ± 50% of the nominal full scale of the active power. The resolution of the
gain is 0.0244%/LSB. See the Current Channel ADC Gain Adjust section.
36h
37h
38h
BAPGAIN
CAPGAIN
AVGAIN
R/W
R/W
R/W
12
12
12
0
0
0
Phase B Active Power Gain Adjust.
Phase C Active Power Gain Adjust.
Phase A Voltage RMS Gain. The apparent power accumulation of the
Phase A can be calibrated by writing to this register. The calibration
range is ± 50% of the nominal full scale of the apparent power. The
resolution of the gain is 0.0244% / LSB. See the Voltage RMS Gain
Adjust section.
39h
3Ah
BVGAIN
CVGAIN
R/W
R/W
12
12
0
0
Phase B Voltage RMS Gain.
Phase C Voltage RMS Gain.
3Bh–
3Dh
Reserved.
3Eh
CHKSUM
R
8
Check Sum Register. The content of this register represents the sum of
all 1s of the latest register read from the SPI port.
3Fh
VERSION
R
8
1
Version of the Die.
* R/W: Read/Write capability of the register.
R: Read-only register.
R/W: Register that can be both read and written.
–34 –
REV. 0
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